Recently, in portable telephone, cable television, communication modem, etc., digital modulation is employed, and time division multiple access (hereinafter called TDMA) is widely used in communication control. As the modulator, a filter device is used for limiting the frequency band. In the filter device, a memory is often used for reducing the circuit size.
FIG. 6 shows a conventional filter device using a memory. Input signal data 100 is entered in an n-bit shift register 8. The output of the shift register 8 is used as a higher address of a memory 5. A signal generated in an address control circuit 4 is used in a lower address of the memory 5. The output of the memory 5 is converted into an analog signal by a digital to analog converter (hereinafter called D/A converter) 6.
Supposing n different impulse response waveforms corresponding to 1 or 0 of the data of each bit position of the shift register 8 to be generated, each bit of the shift register 8 combined with the waveform interference given to a specific bit position j (1.ltoreq.j.ltoreq.n) is digitized. The information to be stored in the memory 5 is this digitized data, and it is converted into an analog signal by the D/A converter 6. The signal generated in an address control circuit 4 used in the lower address of the memory 5 is for over-sampling the analog output signal of the D/A converter 6 for a period of input of next data at time t+1, from the state of the shift register 8 at a certain time t.
When the output of the shift register 8 accesses the memory 5, the waveform interference of the impulse response waveform of each bit position on the specific bit position j can be issued, and the filter device characteristic can be designed by design of information stored in the memory 5.
Thus, the filter device can be composed in a circuit constitution using a memory.
FIG. 7 shows other prior art of filter device using a memory. Input signal data 100 is entered in an n-bit shift register 27. The output of the shift register 27 is used as a higher address of a memory 14. The signal generated in an address control circuit 18 is used in a lower address of the memory 14. The output of the memory 14 is converted into an analog signal by a D/A converter 17.
Each one of n different impulse response waveforms corresponding to 1 or 0 of the data of each bit position of the shift register 27 is digitized by combining with the waveform interference given to a specific bit position (1.ltoreq.j.ltoreq.n). The information to be stored in the memory 14 is this digitized data, and it is converted into an analog signal by the D/A converter 17. The signal generated in an address control circuit 18 used in the lower address of the memory 14 is for over-sampling the analog output signal of the D/A converter 17 for a period of input of next data at time t+1, from the state of the shift register 27 at a certain time t.
By accessing the memory 14 by the output of the shift register 27, the waveform interference of the impulse response waveform of each bit position on the specific bit position j can be issued, and the filter characteristic can be designed by design of information stored in the memory 14.
Thus, in the circuit constitution using the memory 14, the circuit size can be reduced as compared with the circuit using a multiplier.
However, the TDMA is a method of transmission by repeating transmission and stop of output signals of the modulator in a burst manner. Accordingly, in the prior art as shown in FIG. 6, the output of the filter device is changed drastically by transmitting or stopping. As a result, numerous large-peak signals are generated in a wide frequency band, and a significant interference is caused on other channels remote in frequency, and many errors are generated. Therefore, in such prior art as shown in FIG. 6, the performance as the modulator cannot be guaranteed.
Or, in the case of the filter device as shown in FIG. 7, the circuit size is determined by the memory size, that is, the number of stages of the shift register 27. However, the number of stages of the shift register 27 determines the performance indices of the modulator such as the modulation precision, and it cannot be curtailed extremely. Downsizing of circuit is the most important design element for the filter device. However, in the prior art shown in FIG. 7, when the number of stages of the shift register 27 is curtailed, the performance of the modulator such as modulation precision deteriorates, and the performance as the modulator cannot be assured.
The invention is devise d in the light of the above problems, and it is hence an object thereof to remove the defects of the prior arts, and prevent drastic changes of output modulation signal and assure the performance as the modulator if transmission and stop of the output modulation signal are repeated frequently by using the TDMA in the communication control.
It is also an object of the invention to prevent deterioration of performance such as modulation precision and assure the performance as modulator if the circuit size is reduced by curtailing the number of stages of the shift register.